OK, so the above was at a signal vector of 256, whereby I couldn’t go above ~ 43 bpm before the locked phasor freaked out.
At a signal vector size of 64, I can get up to about 180 bpm before it all goes pear-shaped – but the clock is out by 11 ms @ 120 bpm (see pics).
The theoretical period is 125 ms; a free running phasor~ gets close enough, but with the locked phasor~ it’s around 114!
I know timer isn’t sample accurate, but shouldn’t the error still be the same for both the free running and the locked phasor~? So why is the locked phasor~ so far out?
Is it possible to get an accurate clock this way from a transport locked phasor~, or should I just give up?