Control Voltage Theory
Nov 18 2013 | 11:16 pm
I'm looking at Stretta's patch for Midi CC to control voltage and I noticed this small section which I don't quite understand.
The loadmess sends a bang which resets the frequency of phasor~ to 0hz, so why is the inital frequency set to 660hz? Which frequency is actually being outputted in this scenario?
I'm not sure I understand how the phasor interacts with the cycle~'s phase either - cycle~ is set to 0 and so the phasor~ determines the frequency of the sine wave, but how does this effect the output? When sending CV why would you want the waveform to cycle (unless its an LFO)? Does it cycle in this case?
Sorry for the overload of questions, hopefully somebody will be able to explain the theory behind this.
- Nov 18 2013 | 11:18 pmThe patch in question, I'm referring to the section right at the bottom
- Nov 18 2013 | 11:33 pm> The loadmess sends a bang which resets the frequency of phasor~ to 0hz, so why is the inital frequency set to 660hz? Which frequency is actually being outputted in this scenario?0Hz because it's received after being initiated with 660. That means the current value (0) is held.>I’m not sure I understand how the phasor interacts with the cycle~’s phase either – cycle~ is set to 0 and so the phasor~ determines the frequency of the sine wave, but how does this effect the output?0 is received in in cycle's phase inlet so it will output a steady 1. If phasor's frequency was set to something else than 0 it would make cycle run through it's sine wave values.> When sending CV why would you want the waveform to cycle (unless its an LFO)?Lots of reasons, LFO being one of 'm. Do it fast enough and you've got an audible oscillator.> Does it cycle in this case?Not as long phasor has a freq of 0Hz. Connect some [number~]'s or [scope~]'s to see what 's going on.
- Nov 18 2013 | 11:42 pmPerfect response, now I understand!Thank you :-)
