I do a lot of stuff with SIMD (SSE) instructions for speed. In Max 4.6 I seemed to be able to assume that signal vectors were 16 byte aligned under Mac OS X (intel or otherwise) and I never ran into trouble.
In Max5 some experimentation suggests that the vectors are probably 8-byte aligned but 16-byte alignment will occur in 50% or so of cases (due to the 8 byte alignment). This means that my code gives me a bad instruction crash when I call it on an unaligned address.
Obviously, I could do unaligned load/storing but in some cases this would probably mean it wasn't worth using SIMD at all. Is there any chance at all of the older vector alignment being available either by default, or as an option in the future?
I notice that in z_dsp, there is now a tantalising set of macros referring to SIMD things that was not there before. This seems to all be off at the moment, but leads me to think we might expect something SIMD related in the near future. One of the things here seems to be for setting minimum vector size for SIMD, which I imagine might have an effect on memory alignment when/if it's implemented.
The best case for me would be for signal vectors to be 16-byte aligned in all cases, as was the case before. I realise this is basically a fairly esoteric request regarding the inner workings of the dsp code, and that I was relying before on something that was never guaranteed by the docs. However, it's probably the only thing preventing me from using Max5 full time at the moment, and I'd love not to have to go back to 4 for certain speed requirements.