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So I've been banging my head against a wall with this. I have a few solutions that work in theory, but all fail in practice.

What I want is two phasors that remain 180 degrees out of phase but each of which only changes frequency on its phase reset (or whilst

The gen~ phasor seems like the perfect candidate for this, ideally I would hold the phase at 0 until the second phasor is back at 180 degrees, but it just doesn't seem to work, like there aren't enough samples in the period - but I'm fairly sure there are.

I've made a quick knock up of my best solution so you can see what I'm talking about, it does seem to work OK if you use a slow ramp between frequency changes, but this isn't really ideal...

synced-phasors-frequency-change-at-phase-reset-only

I've been testing it some more - it's just so inconsistent and erratic. It changes behaviour apparently based on whether that [selector~] object is there. Sometimes at high frequencies it's fine and at low frequencies it's way off and never corrects itself... what is going on??

^that patch does a more accurate job of what your earlier patch did, but i'm still not entirely clear on what you were trying to do, particularly this part:

I would hold the phase at 0 until the second phasor is back at 180 degrees

^neither of our patches do that... but if you look at things through scopes, you see with my patch they stay at 180 reliably(even during a change of slope/frequency in phasor), so there is no time at which one would need to hold at 0.

(an old msp help file used to use inaccurate arguments like '0.1' for sah~.... this was never a professional/accurate way... always something like [delta]->'< 0'->'sah 0' is better to get the exact start of a phasor~ ramp... or you could just use 'change' -> 'latch' like i did, or 'change' -> 'sah 0'.... same thing with using inexact numbers for everything else like '0.49' instead of '0.5' when trying to get something around a 180 phase difference... '> 0.49' in 64-bit floating point world of gen~ will never detect close enough to an exact phase difference of 180-degrees for sample-accurate needs)

we can still make one hold at 0, but see if this works for you first, and if not, you'd want to only hold at 0 when a change in frequency comes in through the inlet of the phasor(rather than trying to guess as to when they're out of phase by all that 'absdiff'->'> 0.49'/'< 0.51' stuff)

Hi thanks for that, but that's not quite the problem I'm having.

First of all it doesn't matter where the phase reset is,

Wrapping the signal is great for very fine accuracy of phase difference but the issue I'm working with is that I don't want EITHER phasor to change the slope of its ramp in the middle of its phase, only when it is

So under my system the two will be out of phase for a fraction of a period whenever the frequency is changed.

I've attached a diagram that hopefully will show what I want to achieve.

Regardless, looking at my patch, have you noticed the inconsistencies in phase difference? Anyone have any idea why that is happening?

Hi, sorry for misunderstanding, the attachment helps alot, thanks.

I think this patch is the closest i can come to what you want without spending hours on it... i'll leave for you to tweak it to perfection :)

this patch does what your pic shows: moving from faster frequencies to slower frequencies, it will zero the second phasor~ after completing a ramp until the 180 degree phase-point and then retrigger at the new frequency...

however, when moving from slower frequencies to faster(a case not shown in your pic), there is a strong chance the second phasor~ will be too slow and will simply retrigger at the 180-degree phase point without completing its ramp... hopefully the patch shows you enough to figure out how to further gate things if you do want each 2nd ramp to finish completely at its previous frequency before changing frequency:

(edit: in my patch, by 'second phasor~' i mean the '+=' which is reset by the first phasor... but you could easily swap this '+=' out with an actual phasor if you'd prefer, might make it easier... (for some reason, additive-accumulators help me imagine the math more easily :p))

Would it be possible to modify this so that the phasor could be reset to 0? So that both phasors would stop at 0 at the end of their respective cycles when a value of zero was sent in? I'm having trouble wrapping my head around it.

sync'ed phasors, frequency change at phase reset only